parse.h File Reference

Contains functions for parsing Verilog modules. More...

#include "defines.h"

Go to the source code of this file.

Functions
void	parse_design (const char *top, const char *output_db)
	Parses the specified design and generates scoring modules.
void	parse_and_score_dumpfile (const char *db, const char *dump_file, int dump_mode)
	Parses VCD dumpfile and scores design.

---

Detailed Description

Contains functions for parsing Verilog modules.

Author:

Trevor Williams (phase1geo@gmail.com)

Date:

11/27/2001

---

Function Documentation

void parse_and_score_dumpfile	(	const char *	db,
		const char *	dump_file,
		int	dump_mode
	)

Parses VCD dumpfile and scores design.

Exceptions:

anonymous

db_do_timestep Throw vcd_parse bind_perform db_read lxt_parse db_write

Reads in specified CDD database file, reads in specified dumpfile in the specified format, performs re-simulation and writes the scored design back to the specified CDD database file for merging or reporting.

Parameters:

	db	Name of output database file to generate
	dump_file	Name of dumpfile to parse for scoring
	dump_mode	Type of dumpfile being used (see Dumpfile Format for legal values)

References bind_perform(), Catch_anonymous, db_do_timestep(), db_read(), db_write(), DEBUG, debug_mode, DUMP_FMT_FST, DUMP_FMT_LXT, DUMP_FMT_VCD, FALSE, fst_parse(), lxt_parse(), isuppl_u::part, print_output(), PROFILE, PROFILE_END, READ_MODE_NO_MERGE, isuppl_u::scored, sim_dealloc(), sim_initialize(), Throw, TRUE, Try, user_msg, USER_MSG_LENGTH, and vcd_parse().

Referenced by command_score().

  { PROFILE(PARSE_AND_SCORE_DUMPFILE);

  assert( dump_file != NULL );

  Try {

#ifdef DEBUG_MODE
    if( debug_mode ) {
      unsigned int rv = snprintf( user_msg, USER_MSG_LENGTH, "========  Reading in database %s  ========\n", db );
      assert( rv < USER_MSG_LENGTH );
      print_output( user_msg, DEBUG, __FILE__, __LINE__ );
    }
#endif

    /* Read in contents of specified database file */
    (void)db_read( db, READ_MODE_NO_MERGE );
  
    /* Bind expressions to signals/functional units */
    bind_perform( TRUE, 0 );

    /* Add static values to simulator */
    sim_initialize();

#ifdef DEBUG_MODE
    if( debug_mode ) {
      unsigned int rv = snprintf( user_msg, USER_MSG_LENGTH, "========  Reading in VCD dumpfile %s  ========\n", dump_file );
      assert( rv < USER_MSG_LENGTH );
      print_output( user_msg, DEBUG, __FILE__, __LINE__ );
    }
#endif
  
    /* Perform the parse */
    switch( dump_mode ) {
      case DUMP_FMT_VCD :  vcd_parse( dump_file );  break;
      case DUMP_FMT_LXT :  lxt_parse( dump_file );  break;
      case DUMP_FMT_FST :  fst_parse( dump_file );  break;
      default           :  assert( (dump_mode == DUMP_FMT_VCD) || (dump_mode == DUMP_FMT_LXT) || (dump_mode == DUMP_FMT_FST) );
    }
    
    /* Flush any pending statement trees that are waiting for delay */
    (void)db_do_timestep( 0, TRUE );

#ifdef DEBUG_MODE
    if( debug_mode ) {
      unsigned int rv = snprintf( user_msg, USER_MSG_LENGTH, "========  Writing database %s  ========\n", db );
      assert( rv < USER_MSG_LENGTH );
      print_output( user_msg, DEBUG, __FILE__, __LINE__ );
    }
#endif

    /* Indicate that this CDD contains scored information */
    info_suppl.part.scored = 1;

    /* Write contents to database file */
    db_write( db, FALSE, FALSE );

  } Catch_anonymous {
    sim_dealloc();
    Throw 0;
  }

  /* Deallocate simulator stuff */
  sim_dealloc();

  PROFILE_END;

}

void parse_design	(	const char *	top,
		const char *	output_db
	)

Parses the specified design and generates scoring modules.

Exceptions:

anonymous

fsm_var_bind race_check_modules Throw bind_perform db_write

Resets the lexer and parses all Verilog files specified in use_files list. After all design files are parsed, their information will be appropriately stored in the associated lists.

Parameters:

	top	Name of top-level module to score
	output_db	Name of output directory for generated scored files

References bind_perform(), Catch_anonymous, db_check_for_top_module(), db_close(), db_write(), DEBUG, debug_mode, dumpvars_file, error_count, FALSE, FATAL, FATAL_WRAP, flag_check_races, fsm_var_bind(), fsm_var_cleanup(), instance_specified, NORMAL, parser_dealloc_sig_range(), ppfilename, print_output(), PROFILE, PROFILE_END, race_check_modules(), reset_lexer(), score_generate_top_dumpvars_module(), sim_dealloc(), stmt_blk_remove(), str_link_add(), strdup_safe, Throw, top_module, TRUE, Try, user_msg, USER_MSG_LENGTH, VLparse(), WARNING, and WARNING_WRAP.

Referenced by command_score().

  { PROFILE(PARSE_DESIGN);

  Try {

    (void)str_link_add( strdup_safe( top ), &modlist_head, &modlist_tail );

    if( use_files_head != NULL ) {

      int parser_ret;

      /* Initialize lexer with first file */
      reset_lexer( use_files_head );

      Try {

        /* Parse the design -- if we catch an exception, remove the temporary ppfilename */
        parser_ret = VLparse();

        if( (parser_ret != 0) || (error_count > 0) ) {
          print_output( "Error in parsing design", FATAL, __FILE__, __LINE__ );
          Throw 0;
        }

      } Catch_anonymous {
        (void)unlink( ppfilename );
        parser_dealloc_sig_range( &curr_urange, FALSE );
        parser_dealloc_sig_range( &curr_prange, FALSE );
        Throw 0;
      }
     
      /* Deallocate any memory in curr_range variable */
      parser_dealloc_sig_range( &curr_urange, FALSE );
      parser_dealloc_sig_range( &curr_prange, FALSE );

#ifdef DEBUG_MODE
      if( debug_mode ) {
        print_output( "========  Completed design parsing  ========\n", DEBUG, __FILE__, __LINE__ );
      }
#endif

      /* Check to make sure that the -t and -i options were specified correctly */
      if( db_check_for_top_module() ) {
        if( instance_specified ) {
          unsigned int rv = snprintf( user_msg, USER_MSG_LENGTH, "Module specified with -t option (%s) is a top-level module.", top_module );
          assert( rv < USER_MSG_LENGTH );
          print_output( user_msg, FATAL, __FILE__, __LINE__ );
          print_output( "The -i option should not have been specified", FATAL_WRAP, __FILE__, __LINE__ );
          Throw 0;
        }
      } else {
        if( !instance_specified ) {
          unsigned int rv = snprintf( user_msg, USER_MSG_LENGTH, "Module specified with -t option (%s) is not a top-level module.", top_module );
          assert( rv < USER_MSG_LENGTH );
          print_output( user_msg, FATAL, __FILE__, __LINE__ );
          print_output( "The -i option must be specified to provide the hierarchy to the module specified with", FATAL_WRAP, __FILE__, __LINE__ );
          print_output( "the -t option.", FATAL_WRAP, __FILE__, __LINE__ );
          Throw 0;
        }
      }

      /* Perform all signal/expression binding */
      bind_perform( FALSE, 0 );
      fsm_var_bind();
  
      /* Perform race condition checking */
      if( flag_check_races ) {
        print_output( "\nChecking for race conditions...", NORMAL, __FILE__, __LINE__ );
        race_check_modules();
      } else {
        print_output( "The -rI option was specified in the command-line, causing Covered to skip race condition", WARNING, __FILE__, __LINE__ );
        print_output( "checking; therefore, coverage information may not be accurate if actual race conditions", WARNING_WRAP, __FILE__, __LINE__ );
        print_output( "do exist.  Proceed at your own risk!", WARNING_WRAP, __FILE__, __LINE__ );
      }

      /* Remove all statement blocks that cannot be considered for coverage */
      stmt_blk_remove();

#ifdef DEBUG_MODE
      if( debug_mode ) {
        print_output( "========  Completed race condition checking  ========\n", DEBUG, __FILE__, __LINE__ );
      }
#endif

    } else {

      print_output( "No Verilog input files specified", FATAL, __FILE__, __LINE__ );
      Throw 0;

    }

    /* Output the dumpvars module, if specified. */
    if( dumpvars_file != NULL ) {
      unsigned int rv = snprintf( user_msg, USER_MSG_LENGTH, "Outputting dumpvars file %s...", dumpvars_file );
      assert( rv < USER_MSG_LENGTH );
      print_output( user_msg, NORMAL, __FILE__, __LINE__ );
      score_generate_top_dumpvars_module( dumpvars_file );
    }

    /* Write contents to baseline database file. */
    db_write( output_db, TRUE, TRUE );

  } Catch_anonymous {
    fsm_var_cleanup();
    sim_dealloc();
    db_close();
    Throw 0;
  }

  /* Deallocate simulator stuff */
  sim_dealloc();

  /* Close database */
  db_close();

#ifdef DEBUG_MODE
  if( debug_mode ) {
    unsigned int rv = snprintf( user_msg, USER_MSG_LENGTH, "========  Design written to database %s successfully  ========\n\n", output_db );
    assert( rv < USER_MSG_LENGTH );
    print_output( user_msg, DEBUG, __FILE__, __LINE__ );
  }
#endif

  PROFILE_END;

}