Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test. Typically in the design verification work flow, a design verification engineer will develop a self-checking test suite to verify design elements/functions specified by a design's specification document. When the test suite contains all of the tests required by the design specification, the test writer may be asking him/herself, "How much logic in the design is actually being exercised?", "Does my test suite cover all of the logic under test?", and "Am I done writing tests for the logic?". When the design verification gets to this point, it is often useful to get some metrics for determining logic coverage. This is where a code coverage utility, such as Covered, is very useful.

Covered reads in the Verilog design files and a VCD, LXT or FST formatted dumpfile from a diagnostic run and generates a database file called a Coverage Description Database (CDD) file, using the score command. Covered's score command can alternatively be used to generate a CDD file and a Verilog module for using Covered as a VPI module in a testbench which can obtain coverage information in parallel with simulation. The resulting CDD file can be merged with other CDD files from the same design to create accummulated coverage, using the merge command. Once a CDD file is created, the user can use Covered to generate various human-readable coverage reports in an ASCII format or use Covered's GUI to interactively look at coverage results, using the report command. Additionally, as part of Covered's score command, race condition possibilities are found in the design files and can be either ignored, flagged as warnings or flagged as errors. By specifying race conditions as errors, Covered can also be used as a race condition checker.

Covered currently supports Verilog-1995, Verilog-2001 (with the exception of config blocks currently), and some SystemVerilog constructs. Metrics that are generated include the following:

  • Line coverage
  • Toggle coverage
  • Memory coverage
  • Combinational logic coverage
  • FSM state and state-transition coverage
  • Assertion (functional) coverage