Covered User's Guide - 0.7.9

Verilog Code Coverage Analyzer

Trevor Williams


Table of Contents

I. Overview
1. Introduction
2. Coverage Metrics
3. Coverage Boundaries
4. Race Condition Checking
5. Inline Attributes
II. Installation
6. Installation
III. Command-line Usage
7. Getting Started
8. Using Covered
9. The score Command
10. The merge Command
11. The report Command
12. The rank Command
13. The exclude Command
14. Reading the Report
15. Debugging
IV. Graphical User Interface
16. Introduction to the GUI
17. Navigating the Main Window
18. Navigating the Line Coverage Window
19. Navigating the Toggle Coverage Window
20. Navigating the Memory Coverage Window
21. Navigating the Combinational Logic Window
22. Navigating the FSM State/State Transition Coverage Window
23. Navigating the Assertion Coverage Window
24. Navigating the Assertion Source Code Window
25. Creating a New CDD
26. Creating an ASCII report file
27. Creating a CDD Ranking Report
28. Navigating the Preferences Window
29. The Exclusion Reason Popup Window
30. Navigating the Wizard Window
31. FAQ
VI. Epilogue
32. Epilogue

List of Figures

2.1. Digraph Version of Example FSM
9.1. Hierarchical Tree View of Example DUT
10.1. Example of Verilog hierarchy to be scored in parallel
17.1. Covered Main Window
17.2. Covered Main Window Highlighting the Menu Bar
17.3. The File Menu
17.4. The CDD Opened File Viewer
17.5. The Close Warning Window
17.6. The Generate Menu List
17.7. The Exit Warning Window
17.8. The Report Menu
17.9. The View Menu
17.10. The Help Menu
17.11. Covered Main Coverage Type View Bar
17.12. Populated Module/Instance Selection Box
17.13. Covered Main Coverage File Viewer
17.14. Covered Main Information Bar
18.1. Example of uncovered line included for line coverage consideration
18.2. Example of uncovered line excluded for line coverage consideration
19.1. Verbose Toggle Window
20.1. Verbose Memory Window
21.1. Example of the verbose combinational logic window
21.2. Example Coverage Output for an Uncovered Event Subexpression
21.3. Example Coverage Output for an Uncovered Unary Subexpression
21.4. Example Coverage Output for an Uncovered Simple AND-type Combinational Subexpression
21.5. Example Coverage Output for an Uncovered Simple OR-type Combinational Subexpression
21.6. Example Coverage Output for an Uncovered Simple Combinational Subexpression
21.7. Example Coverage Output for an Uncovered Complex Combinational Subexpression
21.8. Example of an excluded subexpression
22.1. Verbose FSM Coverage Window
22.2. Example of excluded state transitions
23.1. Verbose Assertion Coverage Window
23.2. Example of excluded ACP
24.1. Assertion Source Viewer Window
25.1. CDD Creation Option Selection Page
25.2. CDD Creation Output Name Page
25.3. CDD Creation Type Page
25.4. CDD Creation Options1 Page
25.5. CDD Creation Options2 Page
25.6. CDD Creation Insert Menubutton
25.7. CDD Creation Library Extension Window
25.8. CDD Creation Define Window
25.9. CDD Creation Parameter Override Window
25.10. CDD Creation FSM Specification Window
25.11. CDD Creation Module Generation Window
25.12. CDD Creation Module Exclusion Window
25.13. CDD Creation Output Window
26.1. Report Generation Option Selection Page
26.2. Report Generation Options Page
27.1. CDD Ranking Option Selection Page
27.2. CDD Ranking Options Page
27.3. CDD Ranking Input File Selection Page
27.4. CDD Ranking Command Output Page
27.5. CDD Ranking Report Page
28.1. Main Preferences Window
28.2. Coverage Goals Window
28.3. Syntax Highlighting Preferences Pane
28.4. Exclusion Preferences Pane
28.5. Merging Preferences Pane
29.1. The Exclusion Reason Popup Window
29.2. Full View of the Exclusion Reason Popup Window
30.1. Covered GUI Wizard Window

List of Tables

8.1. Global Options to Covered
9.1. Options to score Command
10.1. Options to merge Command
11.1. Options to report Command
12.1. Options to rank Command
13.1. Options to the exclude command
15.1. CLI Command-line Options
28.1. Location of Written .coveredrc File According to the Location of Read .coveredrc File

List of Examples

2.1. Line Coverage Code Sample
2.2. Toggle Coverage Code Sample
2.3. Memory Coverage Code Sample
2.4. Combinational Logic Coverage Code Sample
2.5. FSM Coverage Code Sample
4.1. Using a Race Condition Pragma
5.1. Module Containing an Embedded FSM
5.2. FSM Attribute Code Sample
7.1. Running Covered Alongside a Simulation Process Using a Unix FIFO to Pass Dumpfile Information
9.1. Inline Pragmas to Turn Coverage Exclusion On/Off
9.2. Example of Embedded Coverage On/Off Pragmas
12.1. Rank Output With No Required Files
12.2. Rank Output With Required Files
18.1. Line Coverage Example