Covered: Verilog Code-Coverage Analyzer


This document is meant to be a living document, that is, it is subject to change and updates as the project continues and evolves. There may be incomplete information in certain portions of this documentation that will be filled in with more detail as the code is these areas stabilize.

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Generated on Sun Nov 21 00:55:34 2010 for Covered by  doxygen 1.6.3